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| KS86C4004/P4004/C4104/P4104 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM87RI PRODUCT FAMILY Samsung's SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. KS86C4004/C4104 MICROCONTROLLER The KS86C4004/C4104 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM87Ri CPU core. The KS86C4004/C4104 is a versatile microcontroller, with its A/D converter and a zero-crossing detection capability it can be used in a wide range of general purpose applications. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The KS86C4004/C4104 has 4-Kbytes of program memory on-chip (ROM) and 208-bytes of general purpose register area RAM. Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core: -- Four configurable I/O ports (KS86C4004: 22 pins, KS86C4104: 16 pins) -- Six interrupt sources with one vector and one interrupt level -- Two 8-bit timer/counter with various operating modes -- Analog to digital converter (KS86C4004: 8-bit, 8-channel, KS86C4104: 10-bit, 5-channel) -- One zero cross detection module The KS86C4004/C4104 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, PWM, ADC, ZCD and capture functions. KS86C4004 is available in a 30-pin SDIP and a 32-pin SOP package. KS86C4104 is available in a 24-pin SDIP and a 24-pin SOP package. OTP The KS86P4004/P4104 is an OTP (one time programmable) version of the KS86C4004/C4104 microcontroller. The KS86P4004/P4104 has on-chip 4-Kbyte one-time programmable EEPROM instead of masked ROM. The KS86P4004/P4104 is fully compatible with the KS86C4004/C4104, in function, in D.C. electrical characteristics and in pin configuration. 1-1 PRODUCT OVERVIEW KS86C4004/P4004/C4104/P4104 FEATURES CPU * SAM87Ri CPU core Timer/Counter * * Memory * * 4-Kbyte internal program memory (ROM) 208-byte general purpose register area (RAM) * One 8-bit basic timer for watchdog function One 8-bit timer/counter with three operating modes (10-bit PWM 1ch) One 8-bit timer/counter for the zero-crossing detection circuit Instruction Set * * 41 instructions IDLE and STOP instructions added for power-down modes. Zero-Crossing Detection Circuit * Zero-crossing detection circuit that generates a digital signal in synchronism with an AC signal input Instruction Execution Time * 600 ns at 10 MHz fOSC (minimum) Buzzer Frequency Range * 200 Hz to 20 kHz signal can be generated Interrupts * 6 interrupt sources with one vector and one level interrupt structure Operating Temperature Range * - 40C to + 85C Operating Voltage Range * 2.7 V to 5.5 V Oscillation Frequency * * * 1 MHz to 10 MHz external crystal oscillator Maximum 10 MHz CPU clock 4 MHz RC oscillator OTP Interface Protocol Spec * Serial OTP Package Types General I/O * * Four I/O ports (22 pins for KS86C4004, 16 pins for KS86C4104) Bit programmable ports * * 30-pin SDIP, 32-pin SOP for KS86C4004/P4004 24-pin SDIP, 24-pin SOP for KS86C4104/P4104 A/D Converter * * * Eight analog input pins 8-bit conversion resolution (KS86C4004) 10-bit conversion resolution (KS86C4104) 1-2 KS86C4004/P4004/C4104/P4104 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7 P1.0-P1.3 /ZCD,BUZ,T0,CLO BASIC TIMER XIN XOUT PORT 0 PORT 1 OSC I/O PORT I/O and INTERRUPT CONTROL P2.0-P2.3 /INT0-INT1 /ADC6-ADC7 T0(PWM) TIMER 0 PORT 2 P1.1/BUZ TIMER 1 SAM87RI CPU ADC0 -ADC7 ADC PORT 3 P3.0-P3.5 /ADC0-ADC5 P1.0/ ZCD ZCD 4-KB ROM 208-BYTE REGISTER FILE Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW KS86C4004/P4004/C4104/P4104 PIN ASSIGNMENTS VSS XIN XOUT TEST P0.1 P0.0 RESET P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 KS86C4004 30-SDIP (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P1.3 / CLO P2.0 / INT0 P2.1 / INT1 P2.2 / ADC6 P2.3 / ADC7 Figure 1-2. Pin Assignment Diagram (30-Pin SDIP Package) 1-4 KS86C4004/P4004/C4104/P4104 PRODUCT OVERVIEW VSS XIN XOUT TEST P0.1 P0.0 RESET NC P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 KS86C4004 32-SOP (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 NC P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P1.3 / CLO P2.0 / INT0 P2.1 / INT1 P2.2 / ADC6 P2.3 / ADC7 Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package) 1-5 PRODUCT OVERVIEW KS86C4004/P4004/C4104/P4104 VSS XIN XOUT TEST P0.1 P0.0 RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 KS86C4104 24-SDIP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P2.0 / INT0 AVref AVSS Figure 1-4. Pin Assignment Diagram (24-Pin SDIP Package) 1-6 KS86C4004/P4004/C4104/P4104 PRODUCT OVERVIEW VSS XIN XOUT TEST P0.1 P0.0 RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 KS86C4104 24-SOP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P2.0 / INT0 AVref AVSS Figure 1-5. Pin Assignment Diagram (24-Pin SOP Package) 1-7 PRODUCT OVERVIEW KS86C4004/P4004/C4104/P4104 PIN DESCRIPTIONS Table 1-1. KS86C4004/C4104 Pin Descriptions Pin Names P0.0-P0.7 Pin Type I/O Pin Description Bit-programmable I/O port for normal input or push-pull, open-drain output. Pull-up resistors are assignable by software. Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 1 pins can also be used as alternative functions. Bit-programmable I/O port for Schmitt trigger input or push-pull, open drain output. Pull up resistors are assignable by software. Port 2 can also be used as external interrupt, A/D input. Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 3 pins can also be used as A/D converter input. Crystal/ceramic, or RC oscillator signal for system clock. External interrupt input. System RESET signal input pin. Test signal input pin (for factory use only: must be connected to VSS) Voltage input pin and ground A/D converter reference voltage input and ground Zero crossing detector input 200 Hz-20 kHz frequency output for buzzer sound Timer 0 capture input or 10-bit PWM output System clock output port A/D converter input Circuit Type E-2 Share Pins P1.0-P1.3 I/O P2.0-P2.3 I/O F D D D E E-1 ZCD BUZ T0(PWM) CLO INT0-INT1 ADC6-ADC7 P3.0-P3.5 I/O F ADC0-ADC5 XIN, XOUT INT0-INT1 RESET - - E B - - - F D D D F E-1 - P2.0-P2.1 - - - - P1.0 P1.1 P1.2 P1.3 P3.0-P3.5 P2.2-P2.3 TEST VDD, VSS AVREF, AVSS ZCD BUZ T0 CLO ADC0-ADC7 I I I - - I O I/O O I NOTE: Port 0.7, P1.3, P2.1-P2.3 and P3.5 is not available in KS86C4104/P4104 . 1-8 KS86C4004/P4004/C4104/P4104 PRODUCT OVERVIEW PIN CIRCUITS VDD VDD P-CHANNEL IN N-CHANNEL DATA P-CHANNEL OUT N-CHANNEL OUTPUT DISABLE Figure 1-6. Pin Circuit Type A Figure 1-8. Pin Circuit Type C VDD PULL-UP RESISTOR PULL-UP RESISTOR RESISTOR ENABLE DATA CIRCUIT TYPE C VDD P-CHANNEL IN OUTPUT DISABLE DATA IN/OUT Figure 1-7. Pin Circuit Type B Figure 1-9. Pin Circuit Type D 1-9 PRODUCT OVERVIEW KS86C4004/P4004/C4104/P4104 VDD VDD PNE PULL-UP RESISTOR VDD PNE VDD PULL-UP RESISTOR P-CH PULL-UP ENABLE IN/OUT DATA P-CH PULL-UP ENABLE IN/OUT DATA N-CH OUTPUT DISABLE N-CH OUTPUT DISABLE INPUT INPUT Figure 1-10. Pin Circuit Type E Figure 1-10. Pin Circuit Type E-2 VDD VDD PNE PULL-UP RESISTOR VDD PULL-UP RESISTOR PULL-UP ENABLE VDD DATA IN/OUT N-CH OUTPUT DISABLE OUTPUT DISABLE DIGITAL INPUT DIGITAL INPUT ANALOG INPUT ANALOG INPUT CIRCUIT TYPE C IN/OUT P-CH PULL-UP ENABLE DATA Figure 1-11. Pin Circuit Type E-1 Figure 1-12. Pin Circuit Type F 1-10 KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA 13 OVERVIEW ELECTRICAL DATA In this section, the following KS86C4004/C4104 electrical characteristics are presented in tables and graphs: -- Absolute maximum ratings -- D.C. electrical characteristics -- A.C. electrical characteristics -- Oscillator characteristics -- Oscillation stabilization time -- Operating Voltage Range -- Schmitt trigger input characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by a RESET -- A/D converter electrical characteristics -- Zero-crossing detector -- Zero Crossing Waveform Diagram 13-1 ELECTRICAL DATA KS86C4004/P4004/C4104/P4104 Table 13-1. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Output voltage Output current high Output current low Operating temperature Storage temperature TA TSTG I OL Symbol VDD VI VO I OH All input ports All output ports One I/O pin active All I/O pins active One I/O pin active Total pin current for ports 1, 2, 3 Total pin current for ports 0 - - Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 + 200 - 40 to + 85 - 65 to + 150 C C Unit V V V mA mA Table 13-2. DC Electrical Characteristics (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage Output low voltage VOH VOL1 VOL2 RESET Conditions Ports 1,2,3, and Port 0 XIN and XOUT Ports 1,2,3, and RESET Min 0.8 VDD 0.7 VDD VDD -0.1 Typ - Max VDD Unit V VDD= 2.7 to 5.5 V VDD= 2.7 to 5.5 V - - 0.2 VDD 0.3 VDD 0.1 V Port 0 XIN and XOUT IOH = - 1 mA ports 0, 1, 2, 3 IOL = 15 mA port 0 IOL = 4 mA port 1,2,3 VDD= 4.5 to 5.5 V VDD= 4.5 to 5.5 V VDD= 4.5 to 5.5 V VDD - 1.0 - - 0.4 0.4 - 2.0 2.0 V V 13-2 KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA Table 13-2. DC Electrical Characteristics (Continued) (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V) Parameter Input high leakage current Symbol ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Pull-up resistors ILOH ILOL RP Conditions All inputs except ILIH2 VIN = VDD XIN, XOUT All inputs except ILIL2 and RESET XIN, XOUT All outputs All outputs VIN = 0 V Ports 0-3 VIN = VDD VIN = 0 V VIN = 0 V VOUT = VDD VOUT = 0 V VDD = 5 V VDD = 3 V Supply current IDD1 Run mode 10 MHz CPU clock 8 MHz CPU clock IDD2 Idle mode 10 MHz CPU clock 8 MHz CPU clock IDD3 Stop mode VDD = 5 V 10% VDD = 3 V 10% VDD = 5 V 10% VDD = 3 V 10% VDD = 5 V 10% VDD = 3 V 10% NOTE: D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up resisters, output port drive current, ZCD and ADC. Min - Typ - Max 1 20 Unit A - - -1 - 20 A - - 30 30 - - - 47 280 7.5 3 2 0.7 0.1 2 -2 70 350 15 6 5 2.5 5 A A k mA A 13-3 ELECTRICAL DATA KS86C4004/P4004/C4104/P4104 Table 13-3. AC Electrical Characteristics (TA = -20C to + 85C, VDD = 2.7 V to 5.5 V) Parameter Interrupt input high, low width input low width ZCD noise filter Symbol tINTH, tINTL tRSL - Conditions Port 2 VDD = 5V 10% Input VDD = 5V 10% Min - - Typ 200 1 Max - - Unit ns s 1 t CPU t NF1L t RSL tNF1H tNF2 0.8 VDD 0.2 VDD NOTE: The unit t CPU means one CPU clock period. Figure 13-1. Input Timing Measurement Points 13-4 KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA Table 13-4. Oscillator Characteristics (TA = - 40C to + 85C) Oscillator Main crystal or ceramic C1 Clock Circuit XIN XOUT Test Condition VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V Min 1 1 Typ - - Max 10 8 Unit MHz C2 External clock XIN XOUT VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V 1 1 - - 10 8 RC oscillator XIN R XOUT VDD = 4.75 to 5.25 V R = 8.2K - 4 (P1.3/ CLO) - Table 13-5. Oscillation Stabilization Time (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V) Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization wait time fOSC > 1.0 MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input high and low width (tXH, tXL) tWAIT when released by a reset (1) tWAIT when released by an interrupt (2) Test Condition Min - - 25 - - Typ - - - 216/fOSC - Max 20 10 500 - - ns ms Unit ms NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the in the basic timer control register, BTCON. settings 13-5 ELECTRICAL DATA KS86C4004/P4004/C4104/P4104 CPU CLOCK 10 MHz 8 MHz 4 MHz 3 MHz 2 MHz 1 MHz 1 2 2.7 3 4 5 5.5 6 7 SUPPLY VOLTAGE (V) Figure 13-2. Operating Voltage Range Vout VDD A = 0.2 V DD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD VSS A B C D Vin 0.3 V DD 0.7 V DD Figure 13-3. Schmitt Trigger Input Characteristics Diagram 13-6 KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA Table 13-6. Data Retention Supply Voltage in Stop Mode (TA = - 40C to + 85C, VDD = 2.7 V to 5.5V) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode; VDDDR = 2.0 V Min 2.0 - Typ - 0.1 Max 5.5 5 Unit V A NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. INTERNAL RESET STOP MODE DATA RETENTION MODE IDLE MODE (BASIC TIMER ACTIVE) VDD VDDDR RESET EXECUTION OF STOP NORMAL OPERATING MODE 0.8 V DD 0.2 V DD tWAIT NOTE: tWAIT is the same as 4096 x 16 x 1/f OSC Figure 13-4. Stop Mode Release Timing When Initiated by a RESET 13-7 ELECTRICAL DATA KS86C4004/P4004/C4104/P4104 Table 13-7. A/D Converter Electrical Characteristics (KS86C4004) (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Total accuracy Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time(1) Analog input voltage Analog input impedance ADC reference voltage ADC reference ground Analog input current ADC block current (2) ILE Symbol Test Conditions VDD = 5.12 V CPU clock = 10 MHz AVREF = 5.12 V AVSS = 0 V Min - Typ - - KS86C4004: 8-bit ADC Max 2 1.5 1 2 2 - AVREF - VDD VSS + 0.3 10 s V M V V A mA Unit LSB DLE EOT EOB tCON VIAN RAN AVREF AVSS IADIN IADC - -1 -1 fcpu = 10 MHz - - - - AVREF = VDD = 5 V conversion time = 5 s AVREF = VDD = 5 V conversion time = 5 s AVREF = VDD = 3 V conversion time = 5 s AVREF = VDD = 5 V Power down mode 5 AVSS 2 2.5 VSS - - - - - - - - 1 3 0.5 1.5 - 100 500 nA NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 13-8 KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA Table 13-8. A/D Converter Electrical Characteristics (KS86C4104) (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Resolution Total accuracy Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time (1) KS86C4104: 10-bit ADC Min - - Typ 10 - - Max - 3 2 1 3 2 - s Unit bit LSB Symbol Test Conditions VDD = 5.12 V ILE CPU clock = 10 MHz AVREF = 5.12 V AVSS = 0 V DLE EOT EOB tCON VIAN RAN AVREF - 1 0.5 10-bit conversion 50 x 4/ fOSC (3) - - - 20 - Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current Analog block current (2) AVSS 2 2.5 - - - AVREF - VDD V M V AVSS IADIN IADC - AVREF = VDD = 5 V conversion time = 20 s AVREF = VDD = 5 V conversion time = 20 s AVREF = VDD = 3 V conversion time = 20 s AVREF = VDD = 5 V when power down mode VSS - - - VSS + 0.3 10 V A mA 1 3 0.5 1.5 mA 100 500 nA NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 3. fOSC is the main oscillator clock. 13-9 ELECTRICAL DATA KS86C4004/P4004/C4104/P4104 Table 13-9. Zero Crossing Detector (TA = - 40C to + 85C, VDD = 4.5 V to 5.5 V, VSS = 0 V) Parameter Zero-crossing detection input voltage Zero-crossing detection accuracy Symbol VZC Test Conditions AC connection c = 0.1 F fZC = 60 Hz (sine wave) VDD = 5 V fOSC = 10 MHz fZC - 40 - 200 Hz Min 1.0 Typ - Max 3.0 Unit Vp-p VAZC - - 150 mV Zero-crossing detection input frequency 1/fZC AC Input VAZC VAZ(P-P) ZCINT Figure 13-5. Zero Crossing Waveform Diagram 13-10 KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA 70 VDD = 5.5 V 60 VDD = 5.0 V 50 VDD = 4.5 V 40 I OL (mA) 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (V) 3.5 4.0 4.5 5.0 5.5 Figure 13-6. IOL vs. VOL (P0, TA = 25 C) 13-11 ELECTRICAL DATA KS86C4004/P4004/C4104/P4104 50 VDD = 5.5 V 40 I OL (mA) 30 VDD = 5.0 V VDD = 4.5 V 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (V) 3.5 4.0 4.5 5.0 5.5 Figure 13-7. IOL vs. VOL (P1-P3, TA = 25 C) 13-12 KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA - 36 - 32 - 28 - 24 20 I OH - (mA) - 16 VDD = 5.5 V - 12 -8 -4 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOH (V) 3.5 4.0 4.5 5.0 5.5 VDD = 5.0 V VDD = 4.5 V Figure 13-8. IOH vs. VOH (P0, TA = 25 C) 13-13 ELECTRICAL DATA KS86C4004/P4004/C4104/P4104 - 24 - 20 - 16 - 12 -8 -4 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOH (V) 3.5 4.0 4.5 5.0 5.5 VDD = 5.5 V VDD = 5.0 V VDD = 4.5 V I OH (mA) Figure 13-9. IOH vs. VOH (P1-P3, TA = 25 C) 13-14 KS86C4004/P4004/C4104/P4104 MECHANICAL DATA 14 OVERVIEW 8.94 0.2 MECHANICAL DATA The KS86C4004/C4104 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package (32-SOP-450A), a 24-pin SDIP package (24-SDIP-300) and a 24-pin SOP package (24-SOP-375). Package dimensions are shown in Figures 14-1, 14-2, 14-3, and 14-4. #30 #16 0-15 10.16 #1 27.88 MAX 27.48 0.2 #15 3.81 0.2 5.08MAX (1.30) 1.12 0.1 1.778 NOTE: Dimensions are in millimeters. Figure 14-1. 30-Pin SDIP Package Dimensions 3.30 0.3 0.51MIN 0.56 0.1 0.25 +0.1 - 0.0 30-SDIP-400 5 14-1 MECHANICAL DATA KS86C4004/P4004/C4104/P4104 0~8 #32 #17 12.00 0.3 8.34 0.2 32-SOP-450A 11.43 +0.10 #1 #16 0.20 - 0.05 2.00 0.2 19.90 0.2 (0.43) 0.40 0.1 1.27 NOTE: Dimensions are in millimeters. Figure 14-2. 32-SOP-450A Package Dimensions 14-2 0.0MIN 2.40MAX 0.10 MAX 0.78 0.2 KS86C4004/P4004/C4104/P4104 MECHANICAL DATA #24 #13 0-15 6.40 0.2 7.62 24-SDIP-300 #1 23.35 MAX 22.95 0.2 #12 3.25 0.2 5.08MAX 0.46 0.1 (1.69) 0.89 0.1 1.778 NOTE: Dimensions are in millimeters. Figure 14-3. 24-SDIP-300 Package Dimensions 3.30 0.3 0.51MIN 0.25 +0.1 - 0.05 14-3 MECHANICAL DATA KS86C4004/P4004/C4104/P4104 0-8 #24 #13 10.30 0.3 7.50 0.2 9.53 +0.10 24-SOP-375 #1 #12 0.15 - 0.05 15.34 0.2 2.30 0.2 (0.69) 0.38 0.1 1.27 NOTE: Dimensions are in millimeters. Figure 14-4. 24-SOP-375 Package Dimensions 14-4 0.05MIN 2.70MAX 15.74 MAX 0.10 MAX 0.850.20 KS86C4004/P4004/C4104/P4104 KS86P4004/P4104 OTP 15 OVERVIEW KS86P4004/P4104 OTP The KS86P4004/P4104 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS86C4004/C4104 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The KS86P4004/P4104 is fully compatible with the KS86C4004/C4104 , both in function and in pin configuration. Because of its simple programming requirements, the KS86P4004/P4104 is ideal for use as an evaluation chip for the KS86C4004/C4104 . VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 RESET/ RESET P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 KS86P4004 30-SDIP (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P0.7 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P1.3/CLO P2.0/INT0 P2.1/INT1 P2.2/ADC6 P2.3/ADC7 NOTE: The bolds indicate an OTP pin name. Figure 15-1. Pin Assignment Diagram (30-Pin SDIP Package) 15-1 KS86P4004/P4104 OTP KS86C4004/P4004/C4104/P4104 VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 RESET/ RESET NC P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 KS86P4004 32-SOP (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P0.7 NC P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P1.3/CLO P2.0/INT0 P2.1/INT1 P2.2/ADC6 P2.3/ADC7 NOTE: The bolds indicate an OTP pin name. Figure 15-2. Pin Assignment Diagram (32-Pin SOP Package) 15-2 KS86C4004/P4004/C4104/P4104 KS86P4004/P4104 OTP VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 RESET/ RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 KS86P4104 24-SDIP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P2.0/INT0 AVref AVSS NOTE: The bolds indicate an OTP pin name. Figure 15-3. Pin Assignment Diagram (24-Pin SDIP Package) 15-3 KS86P4004/P4104 OTP KS86C4004/P4004/C4104/P4104 VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 RESET/ RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 KS86P4104 24-SOP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P2.0/INT0 AVref AVSS NOTE: The bolds indicate an OTP pin name. Figure 15-4. Pin Assignment Diagram (24-Pin SOP Package) 15-4 KS86C4004/P4004/C4104/P4104 KS86P4004/P4104 OTP Table 15-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P0.3 Pin Name SDAT Pin No. KS86P4004: 28 (30) KS86P4104: 22 (22) KS86P4004: 29 (31) KS86P4104: 23 (23) 4 During Programming I/O I/O Function Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned Serial clock pin (input only pin) Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) P0.2 TEST SCLK VPP (TEST) I/O I RESET RESET 7 KS86P4004: 30 (32) / 1 KS86P4104: 24 (24) / 1 I I Chip Initialization Logic power supply pin. VDD/VSS VDD/VSS NOTE: ( ) means the SOP OTP pin number. Table 15-2. Comparison of KS86P4004/P4104 and KS86C4004/C4104 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability KS86P4004/P4104 4-Kbyte EPROM 2.7 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 30 SDIP/32 SOP/24 SDIP/24 SOP User Program 1 time Programmed at the factory KS86C4004/C4104 4-Kbyte mask ROM 2.7 V to 5.5 V OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the KS86P4004/P4104, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria VDD 5V VPP REG/MEM 0 0 0 1 ADDRESS R/W 1 0 1 0 MODE EPROM read EPROM program EPROM verify EPROM read protection (TEST) 5V 12.5 V 12.5 V 12.5 V (A15-A0) 0000H 0000H 0000H 0E3FH NOTE: "0" means Low level; "1" means High level. 15-5 KS86P4004/P4104 OTP KS86C4004/P4004/C4104/P4104 NOTES 15-6 |
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